Why can't it be? Of course, designing hardware is different from writing software, but it's important to realize that these new age HDLs aren't really HDLs in the strictest a sense but rather languages that let you cleanly write RTL generator programs.
It's exactly I love most about Chisel: it's like having a Verilog preprocessor which wasn't hacked together in twenty minutes as an afterthought.
> these new age HDLs aren't really HDLs in the strictest a sense but rather languages that let you cleanly write RTL generator programs
At what point does the abstraction start to help your productivity in developing gateware, rather than hamper it?
I’ve heard more than a few horror stories from gateware devs trying to untangle HDL generated by something like Matlab, Simulink, or even HLS tools like Vitis.
> It's exactly I love most about Chisel
Would love to hear more about your experience with Chisel. I’ve learned just a bit about it from going to conferences at MIT LL. Seems interesting, but at the same time, I’m also an avowed skeptic when it comes to adding more gateware abstractions on top of raw HDL.
It's exactly I love most about Chisel: it's like having a Verilog preprocessor which wasn't hacked together in twenty minutes as an afterthought.