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What tool can you advise me to find the best combination of dividers and multipliers in PLL clocks and dividers in the UART and SPI peripherals so that the deviation from the assumed baudrate is as small as possible and that the dividers meet a number of constraints, including e.g. those from the chip errata which says that one PLL must be 2 times faster than the other?


Write a half page long python script that iterate all combinations , it won't take long, and you have to do that only once


"When in doubt, use brute force." - Ken Thompson


Basically the underlying principle of Prolog.


Excel. Conditionally format based on constrain violations and difference from target baudrate. Brute force and scroll.


I've had good experiences with OptaPlanner:

https://www.optaplanner.org/


Try optlang. It mostly does ILP/LP though.




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