> There is no such phase detector or ADC on this PCB, so it’s a good guess to assume that the TM4313 uses frequency locked loop.
They almost certainly implemented a digital PLL in the micro that compares the 10 MHz clock signal to the 1 PPS output of the GNSS module. Using a frequency lock would lead to a residual drift with respect to the GNSS time scale.
You're absolutely right about the drift, but an FLL is sufficient for cases where you case about the frequency and not about the exact position of the 1PPS output.
E.g. when using a GPSDO to drive or calibrate frequency counters, spectrum analyzers, signal generators, and similar kind of equipment.
There are many GPSDOs out there that are FLL only.
I'm not sure how you'd implement a pure digital-only phase detector inside an LPC1752. The precision of measuring the phase would be pretty terrible when the internal clock is only, say, 100MHz?
Edit: I should be able to check this by putting the GPS module 1PPS and the GPSDO 1PSS output on the scope.
> The LPC1759/58/56/54/52/51 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes
two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.
Time-tagging the transitions of the 1PPS signal (and subtracting 100000000 at each transition) directly gives the phase difference measured in clock cycles. At 100 MHz clock frequency, the resolution is 10 ns which is well below the timing jitter of a GNSS 1PPS output. The OXCO can then be steered using a very slow feedback loop (in order not to spoil its short-term stability).
> At 100 MHz clock frequency, the resolution is 10 ns which is well below the timing jitter of a GNSS 1PPS output.
I own a more expensive GPSDO model from the same vendor and I can confirm that the TIC output is at 10ns resolution. TM4313 is being sold at 1/3 price of mine, I'd be very surprised if its TIC has a higher resolution.
I thought that 10ns was too coarse, when most PLL-based GPSDO get much higher accuracy with 8-bit ADCs. But maybe that just doesn't matter enough when the input jitter is very high to begin with.
Even the simplest TCXO is more stable than the GNSS up to a few ten s. The OCXO has the crossover at a few hundred s, and the Rubidium atomic clock at over one thousand s.
At these time scales, the jitter of the 1PPS measurement averages out very well and should not be a serious limitation.
All PLL-based GPSDO designs that I've seen measure the difference between the rising edge of the 1PPS signal to the next rising edge of the 10MHz clock (or vice versa). You're basically using the kind of analog interpolation that's also used in frequency counters to get sub-10MHz clock cycle granularity. (See here: https://tomverbeure.github.io/2023/06/16/Frequency-Counting-...).
I understand that you can still implement a PLL with a pure digital 10ns counter (I've once designed one to create a 12.288MHz I2S clock out of a very jitters 48kHz audio sample tick), but I'm wondering what the benefits are of using the analog interpolator.
If the input 1PPS signal is so jittery, when do you get diminishing returns in increasing the precision of the pulse-to-pulse measurement?
They almost certainly implemented a digital PLL in the micro that compares the 10 MHz clock signal to the 1 PPS output of the GNSS module. Using a frequency lock would lead to a residual drift with respect to the GNSS time scale.