Every time I see this stuff, I really wish people who understand cpus at this level wrote a modern version of Nand to Tetris, except with a modern CPU and the OS being essentially a micro linux kernel that includes things like networking and graphics.
That would be a non-trivial undertaking. Modern CPUs have a lot of silicon dedicated to branch prediction and fetching RAM to populate caches and so on.
Fetching the data that the hardware threads want so they can do work is a very large portion of what a complete modern day CPU does. Networking and graphics are also complete career paths each in their own right.
When the 6502 is your CPU, it is possible for the entire computer it powers to be understood by a single person, and that's not possible with modern day, high end CPUs, not at the same level of detail. A single self-paced course which covers it all probably isn't realistic, but one for CPU, one for GPU, and one for network, those seem like workable things.
"NAND to Hatris" (NAND to Tetris sequel/expansion?)
Gate-level simulation (even zero-delay, let's not mention delay-aware or even power-aware) for a modern-sized CPU takes weeks just to run through some basic liveliness checks. See [1] for just a taste of gate-level simulation trickiness:
You can do an RV32I in 10k gates, RV64GC in maybe 30k gates? I think the GP meant barely enough to run a thin OS, but not an antique. In-order, small to no cache, you get it.
A visual RV64GC would be a pedagogical tool, not something necessary for a tape out.
