It's disappointing that RISC-V designers swallowed myths that resulted in unpleasant ISA details.
For example, the notion that condition codes interfere with OoO execution has been repudiated; Power and x86 both now rename condition registers. Lack of popcount and rotate in the base instruction set are glaring omissions. (That x86 got popcount late, and that the bitmanip extension will have them if it ever gets ratified, are no excuse.) It was silly to make the compare instruction generate a 1 instead of the overwhelmingly more useful ~0.
We only get a new ISA once in a generation. It is tragic when it is wrong.
It is possible, in principle, that popcount and rotate could be added to the base 16-bit instructions, but I'm not holding my breath.
For example, the notion that condition codes interfere with OoO execution has been repudiated; Power and x86 both now rename condition registers. Lack of popcount and rotate in the base instruction set are glaring omissions. (That x86 got popcount late, and that the bitmanip extension will have them if it ever gets ratified, are no excuse.) It was silly to make the compare instruction generate a 1 instead of the overwhelmingly more useful ~0.
We only get a new ISA once in a generation. It is tragic when it is wrong.
It is possible, in principle, that popcount and rotate could be added to the base 16-bit instructions, but I'm not holding my breath.