Based on these photos, I’d estimate instruction decoder takes about 10% of each core, and about 7% of the whole chip.
For Intel I was unable to find similar pics, but my estimation is 3-4% of the chip area. The instruction set is the same; the complexity should be comparable. But most Intel chips have like 50% of the area occupied by integrated graphics.
The micro-op cache size increased to 2048 from Intel's 1536 μops. His testing shows 5 instructions per clock cycle up from Intel's 4. There are limits to the ILP a scheduler can find; more in one area means more demand in another. This is no mean feat for AMD to pull off.
This article has some annotated pics of AMD Ryzen 7: http://wccftech.com/amd-ryzen-architecture-detailed/
Based on these photos, I’d estimate instruction decoder takes about 10% of each core, and about 7% of the whole chip.
For Intel I was unable to find similar pics, but my estimation is 3-4% of the chip area. The instruction set is the same; the complexity should be comparable. But most Intel chips have like 50% of the area occupied by integrated graphics.