Regarding AVX: could rust be compiled with different symbols that target different x64 instruction sets, then at runtime choose the symbol set that is the more performant for that architecture?

I'm not sure how that works. You either let the compiler compile your whole program with AVX (which duplicates the binary) or you manually use AVX with runtime detection on selected places (which requires writing manual vectorization).

> First Revision - Completed with minimal human contribution (auto-accept mode) > > Second Revision - Planned with increased human-in-the-loop involvement

At least 'minimal human contribution' in the first revision. So scan read it as it revised the book.

I do find it amusing to think that people might just ask an AI to summarize the book instead of actually reading it. Maybe even 'review' it as well.

The future will have authenticity in short supply

> Compilers are not yet rewriting data structures and algorithms based on microarchitecture.

Afaik mojo allows for this with the autotuning capability and metaprogramming

What data type/precision? How much parallelism versus iterative? Is this fully in fabric or part of a SoC? Easy to get mired in many details.

HW design has so many degrees of freedom which makes it fun but challenging.

What specific topics are you trying to address with this?

Showing the tradeoffs between complexity & throughput of HLS and HDL implementations is the goal. I assume, uint8 should be sufficient to make a point?

Newton Raphson could be used to calculate a reciprocal. (in a bit width larger than 8). If starting from a good reciprocal approximation, convergence to bit accurate reciprocal should not take many iterations. Then multiply the reciprocal with the numerator to perform the divide

I worked on an automotive FMCW LiDAR that didn't quite make it to market. Cool technology but it was difficult to scale the cost down, which is pretty important for automotive. Margins are very low in that market

Does anyone have a good summary of the Buck(2) track?

It's also, if not more so, a factor of transistor voltage. 1.1V transistors are less prone to upset events than 0.7V. It's possible (assumption, here) that some 3+ volt circuits are still used for critical components of the system

It would be possible to use much higher supply voltages if silicon were replaced with a semiconductor material having a higher band gap.

The main obstacle that has prevented this until now is that in all high-bandgap semiconductors it is easy to make only transistors of a single polarity, not transistors with both polarities, as required for CMOS logic. For high circuit densities it would be difficult to replace the CMOS logic, because all alternatives have higher idle power consumption.

You could probably post it on http://fpgajobs.com/