| | Reusing the Sony CRT Module of an HP 16500A Logic Analyzer (tomverbeure.github.io) |
| 27 points by picture on Oct 6, 2022 | past | 1 comment |
|
| | Reed-Solomon Error Correcting Codes from the Bottom Up (tomverbeure.github.io) |
| 4 points by hasheddan on Aug 8, 2022 | past |
|
| | HP 16500A Logic Analyzer Teardown (tomverbeure.github.io) |
| 2 points by picture on June 18, 2022 | past |
|
| | GDBWave – A Post-Simulation Waveform-Based RISC-V GDB Debugging Server (tomverbeure.github.io) |
| 13 points by X-Cubed on Feb 21, 2022 | past |
|
| | Video Timings Calculator (tomverbeure.github.io) |
| 2 points by picture on Jan 26, 2022 | past |
|
| | Semihosting, Your PC as Console of an Embedded RISC-V CPU (tomverbeure.github.io) |
| 3 points by picture on Dec 31, 2021 | past |
|
| | Repairing an HP 3478A Multimeter with a Hacksaw (tomverbeure.github.io) |
| 53 points by picture on Nov 26, 2021 | past | 23 comments |
|
| | The Intel JTAG Primitive – Using JTAG Without Virtual JTAG (tomverbeure.github.io) |
| 4 points by picture on Oct 31, 2021 | past |
|
| | VexRiscv, OpenOCD, and Traps (tomverbeure.github.io) |
| 3 points by picture on July 18, 2021 | past |
|
| | Write Your Own C and Python Clients for the Intel JTAG UART (tomverbeure.github.io) |
| 2 points by EntICOnc on May 17, 2021 | past |
|
| | A Pixel Purse LED Cube Controlled by a Cisco 3G Modem (tomverbeure.github.io) |
| 118 points by picture on May 17, 2021 | past | 18 comments |
|
| | Write Your Own C and Python Clients for the Intel JTAG UART (tomverbeure.github.io) |
| 7 points by picture on May 16, 2021 | past |
|
| | The Intel JTAG UART – Add a Serial Console to Your Design Without Extra IO Pins (tomverbeure.github.io) |
| 4 points by picture on May 3, 2021 | past |
|
| | A Hack to Update RAM Initialization Contents in Intel FPGA Bitstreams (tomverbeure.github.io) |
| 67 points by picture on April 26, 2021 | past | 15 comments |
|
| | The $37 Arrow DECA FPGA Board (tomverbeure.github.io) |
| 2 points by picture on April 24, 2021 | past |
|
| | Tesla Model Y Energy Consumption with and Without Bikes on Rack (tomverbeure.github.io) |
| 3 points by leugim on April 19, 2021 | past |
|
| | HP/Agilent E3631A Rotary Knob Repair (tomverbeure.github.io) |
| 70 points by picture on April 16, 2021 | past | 57 comments |
|
| | Getting Started with ECP5 FPGAs on the Colorlight I5 FPGA Development Board (tomverbeure.github.io) |
| 5 points by homarp on Jan 29, 2021 | past |
|
| | Option Hacking the Tektronix TDS 420A (tomverbeure.github.io) |
| 59 points by segfaultbuserr on Nov 11, 2020 | past | 21 comments |
|
| | Cxxrtl, a Yosys Simulation Back End (tomverbeure.github.io) |
| 4 points by homarp on Aug 11, 2020 | past | 2 comments |
|
| | Reverse Engineering the Comtech AHA363 PCIe Gzip Accelerator Board (tomverbeure.github.io) |
| 127 points by todsacerdoti on June 21, 2020 | past | 41 comments |
|
| | Building Multiport Memories with Block RAMs (tomverbeure.github.io) |
| 2 points by matt_d on Aug 4, 2019 | past |
|
| | Racing the Beam: Truly Magnificent HW/SW Hacking (tomverbeure.github.io) |
| 3 points by ttsiodras on June 5, 2019 | past |
|
| | SweRV – An Annotated Deep Dive of the SweRV RISC-V Core (tomverbeure.github.io) |
| 113 points by matt_d on March 14, 2019 | past | 13 comments |
|
| | Under the hood of Formal Verification (tomverbeure.github.io) |
| 3 points by matt_d on Jan 7, 2019 | past |
|
| | Implementing a beam-racing ray tracer from scratch on an FPGA (tomverbeure.github.io) |
| 5 points by mariuz on Dec 12, 2018 | past |
|
| | A Racing-The-Beam Ray Tracer in an FPGA (tomverbeure.github.io) |
| 6 points by corysama on Dec 11, 2018 | past |
|
| | A Bug-Free RISC-V Core Without Simulation (tomverbeure.github.io) |
| 2 points by matt_d on Dec 8, 2018 | past |
|
| | The VexRiscV CPU – A New Way to Design (tomverbeure.github.io) |
| 3 points by matt_d on Dec 7, 2018 | past |
|
